Flip chip technology provides a method for connecting an integrated circuit (IC) die to a substrate within a package or directly to a printed circuit board (PCB). In the flip chip method, a plurality of electrical terminals (pads) are formed on an active face of the die. A respective solder bump is formed on each of the electrical terminals. The package substrate or printed circuit board has a plurality of terminal pads corresponding to the terminals on the die. A plurality of solder bumps are formed, either on the die or on the terminal pads of the package substrate or PCB, on the side facing the die. These bumps can be heated to reflow the solder and form electrical and mechanical connections between the die and the package substrate or PCB. The die is “flipped,” so that the terminals of the device face the terminal pads of the package substrate or printed circuit board. Heat is applied to reflow the solder bumps, forming electrical and mechanical connections between the substrate (or PCB) and the active face of the die. An underfill material can be filled into the space between the die and the substrate (or PCB) to strengthen the die/substrate adhesion, redistribute thermal mismatch loading, and protect the solder connections.
The die and the package substrate or PCB typically have very different coefficients of thermal expansion (CTE) from each other. For example, the CTE of Silicon is between about 2 ppm/C and about 5 ppm/C, the CTE for the organic package substrate may be about 16 ppm/C, and the CTE for solder is typically between about 20 ppm/C and 30 ppm/C. If no underfill material is employed, the flip chip solder bumps provide the only adhesion between the die and the substrate and are fully exposed to the thermal induced stresses. Repeated thermal cycling causes the solder bumps to fail (fatigue failure) by loss of adhesion at the interface or formation of stress induced cracks within the solder bumps. The reliability of the solder bumps is related to the stress/strain behaviors under cyclical thermal deformation. Reducing the stress/strain on solder bumps improves reliability and increases fatigue life. Therefore, it is common to provide an underfill material to fill the gap between the die and the package substrate or printed circuit board.
Typical underfill materials have CTE values between about 30 ppm/C and about 50 ppm/C. The underfill absorbs some of the residual stresses, to reduce the stress within the solder balls, and in the interfaces between the solder balls and the die.
The semiconductor industry is moving towards increasing use of copper metal and low-k dielectric materials in place of aluminum and silicon dioxide. Copper reduces the resistance of the metal interconnect lines (and increases their reliability), while low-k dielectrics (having dielectric constant k less than 3.9, the k value of silicon dioxide) reduce the parasitic capacitance between the metal lines. It is expected that use of low k dielectric materials will increase significantly at the 65 nanometer node, and that use of extreme low-k (ELK) dielectric materials (k between 2.0 and 2.5) will increase significantly at the 45 nanometer node.
The use of low-k dielectric materials in the interconnect layers increases the thermal mismatch problem for flip chip packages. Low-k dielectric materials may have CTE values of about 8 ppm/C., the flip chip package with an underfill generates high stress on the low-k layers and impacts the reliability of low-k/ELK flip chip packages.
The thermal mismatch problem is increased further by the use of lead-free (LF) packages. With LF bumps, solder and intermetallic compounds (alloys) are too brittle and can cause cracking of the bumps.
Current low stress and low glass transition temperature (Tg) underfill materials suitable for eutectic (EU)/high lead (HL) solder cannot adequately protect lead-free bumps. Currently available combinations of LF solder and underfill materials are not suitable for low-k flip chip packages. In packages using a conventional LF solder and low-k dielectric, solder bumps were observed to crack and the substrate traces broke during a temperature cycling test. Underfill delamination was also observed after ball mount and pre-conditioning.
Improved packaging methods and structures are desired.